Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device.
Description of the Related Art
As a method for reducing characteristic variations of a MOS transistor in a semiconductor device, a technique of covering the MOS transistor after gate electrode etching with a protective film is proposed (see Japanese Patent Laid-Open No. 2013-84694).
According to Japanese Patent Laid-Open No. 2013-84694, a protective film is formed through gate electrode etching or process treatment executed subsequently thereto, then process treatment such as formation of a diffusion layer is performed and an insulating film is formed so as to cover the protective film. At this time, the insulating film is formed without removing the protective film.
According to Japanese Patent Laid-Open No. 2013-84694, variations in MOS transistor characteristics are reduced by forming the protective film on a surface of a semiconductor substrate immediately after the gate electrode etching. After forming the protective film, ion implantation is performed on the semiconductor substrate and a diffusion region is formed, and in that case, ion implantation is also performed on a photoresist pattern. However, ashing performed on the ion-implanted photoresist pattern is not particularly taken into consideration. When ashing is performed on the resist pattern, residues of the resist may be generated. Removal of the residues of this resist requires specific cleaning processing. In that case, the protective film which is based on a silicon oxide film is wet-etched and part or the whole thereof is removed, which may consequently cause the loss of the function as the protective film. When there is no protective film, the gate insulating film is wet-etched and part or the whole thereof is removed, which may consequently cause deterioration in the reliability of the transistor.